ARM Cortex-A76 Core User Manual

Traps and enables
For a description of the prioritization of any generated exceptions, see Exception priority order
in the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
exceptions taken to AArch64 state, and see Synchronous exception prioritization for exceptions
taken to AArch64 state.
Write access to this register from EL1 or EL2 depends on the value of bit[0] of ACTLR_EL2 and
ACTLR_EL3.
B2 AArch64 system registers
B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-169
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core