D4.4 PMCR, Performance Monitors Control Register
The PMCR provides details of the Performance Monitors implementation, including the number of
counters implemented, and configures and controls the counters.
Bit field descriptions
PMCR is a 32-bit register, and is part of the Performance Monitors registers functional group.
31 0567 121011151623
IMP X
3424
IDCODE N EPCD
DP
LC
RES0
Figure D4-3 PMCR bit assignments
IMP, [31:24]
Indicates the implementer code. The value is:
0x41 ASCII character 'A' - implementer is Arm Limited.
IDCODE, [23:16]
Identification code. The value is:
0x0B Cortex-A76 core.
N, [15:11]
Identifies the number of event counters implemented.
0b00110 The core implements six event counters.
RES0, [10:7]
RES0 Reserved.
LC, [6]
Long cycle count enable. Determines which PMCCNTR bit generates an overflow recorded in
PMOVSR[31]. The overflow event is generated on a 32-bit or 64-bit boundary. The possible
values are:
0b0 Overflow event is generated on a 32-bit boundary, when an increment changes
PMCCNTR[31] from 1 to 0. This is the reset value.
0b1 Overflow event is generated on a 64-bit boundary, when an increment changes
PMCCNTR[63] from 1 to 0.
Arm deprecates use of PMCR.LC = 0b0.
DP, [5]
Disable cycle counter CCNT when event counting is prohibited. The possible values are:
0b0 Cycle counter operates regardless of the non-invasive debug authentication
settings. This is the reset value.
0b1 Cycle counter is disabled if non-invasive debug is not permitted and enabled.
X, [4]
D4 AArch32 PMU registers
D4.4 PMCR, Performance Monitors Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D4-441
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