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ARM Cortex-A76 Core User Manual

ARM Cortex-A76 Core
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B2.1 AArch64 registers
This chapter provides information about the AArch64 system registers with implementation defined bit
fields and implementation defined registers associated with the core.
The chapter provides implementation specific information, for a complete description of the registers, see
the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The chapter is presented as follows:
AArch64 architectural system register summary
This section identifies the AArch64 architectural system registers implemented in the
Cortex-A76 core that have implementation defined bit fields. The register descriptions for these
registers only contain information about the implementation defined bits.
AArch64 implementation defined register summary
This section identifies the AArch64 architectural registers implemented in the Cortex-A76 core
that are implementation defined.
AArch64 registers by functional group
This section groups the implementation defined registers and architectural system registers with
implementation defined bit fields, as identified previously, by function. It also provides reset
details for key register types.
Register descriptions
The remainder of the chapter provides register descriptions of the implementation defined
registers and architectural system registers with implementation defined bit fields, as identified
previously. These are listed in alphabetic order.
B2 AArch64 system registers
B2.1 AArch64 registers
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-126
Non-Confidential

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ARM Cortex-A76 Core Specifications

General IconGeneral
ArchitectureARMv8.2-A
MicroarchitectureCortex-A76
Pipeline Depth13 stages
FrequencyUp to 3.0 GHz
Process Technology7nm
Core TypeOut-of-order
NEONYes
Power EfficiencyImproved over Cortex-A75
Performance Improvement35% over Cortex-A75
Core Count1-4 cores per cluster
ISA SupportAArch64 and AArch32
Branch PredictionYes
L1 Data Cache32KB, per core
L2 Cache256KB or 512KB, per core
L3 CacheUp to 4MB
Memory SupportLPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)DynamIQ Shared Unit (DSU)
Cryptography ExtensionsYes
Virtualization SupportYes
L1 Cache64 KB per core

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