ARM Cortex-A76 Core User Manual

• B2.78 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1 on page B2-258.
• B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1 on page B2-260.
• B2.80 LORC_EL1, LORegion Control Register, EL1 on page B2-261.
• B2.81 LORID_EL1, LORegion ID Register, EL1 on page B2-262.
• B2.82 LORN_EL1, LORegion Number Register, EL1 on page B2-263.
• B2.83 MDCR_EL3, Monitor Debug Configuration Register, EL3 on page B2-264.
• B2.84 MIDR_EL1, Main ID Register, EL1 on page B2-266.
• B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1 on page B2-267.
• B2.86 PAR_EL1, Physical Address Register, EL1 on page B2-269.
• B2.87 REVIDR_EL1, Revision ID Register, EL1 on page B2-270.
• B2.88 RMR_EL3, Reset Management Register on page B2-271.
• B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3 on page B2-272.
• B2.90 SCTLR_EL1, System Control Register, EL1 on page B2-273.
• B2.91 SCTLR_EL2, System Control Register, EL2 on page B2-275.
• B2.92 SCTLR_EL3, System Control Register, EL3 on page B2-276.
• B2.93 TCR_EL1, Translation Control Register, EL1 on page B2-278.
• B2.94 TCR_EL2, Translation Control Register, EL2 on page B2-279.
• B2.95 TCR_EL3, Translation Control Register, EL3 on page B2-280.
• B2.96 TTBR0_EL1, Translation Table Base Register 0, EL1 on page B2-281.
• B2.97 TTBR0_EL2, Translation Table Base Register 0, EL2 on page B2-282.
• B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3 on page B2-283.
• B2.99 TTBR1_EL1, Translation Table Base Register 1, EL1 on page B2-284.
• B2.100 TTBR1_EL2, Translation Table Base Register 1, EL2 on page B2-285.
• B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2 on page B2-286.
• B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287.
• B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2 on page B2-288.
• B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2 on page B2-289.
B2 AArch64 system registers
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core