B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1
The ID_ISAR4_EL1 provides information about the instruction sets implemented by the core in
AArch32.
Bit field descriptions
ID_ISAR4_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
31 24 23 20 19 16 15 12 11 8 7 4 3 0
SynchPrim_frac
SWP_frac
28 27
PSR_M Barrier SMC WriteBack WithShifts Unpriv
Figure B2-53 ID_ISAR4_EL1 bit assignments
SWP_frac, [31:28]
Indicates support for the memory system locking the bus for SWP or SWPB instructions:
0x0 SWP and SWPB instructions not implemented.
PSR_M, [27:24]
Indicates the implemented M profile instructions to modify the PSRs:
0x0 None implemented.
SynchPrim_frac, [23:20]
This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented
Synchronization Primitive instructions:
0x0 • The LDREX and STREX instructions.
• The CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.
• The LDREXD and STREXD instructions.
Barrier, [19:16]
Indicates the supported Barrier instructions in the A32 and T32 instruction sets:
0x1 The DMB, DSB, and ISB barrier instructions.
SMC, [15:12]
Indicates the implemented SMC instructions:
0x0 None implemented.
WriteBack, [11:8]
Indicates the support for Write-Back addressing modes:
0x1 Core supports all the Write-Back addressing modes as defined in Armv8-A.
WithShifts, [7:4]
Indicates the support for instructions with shifts.
B2 AArch64 system registers
B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-241
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