D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0
The activity counters AMEVTYPER_EL0n are directly accessible in the memory mapped view. n is 0-4.
Bit field descriptions
The AMEVTYPERn_EL0 is a 32-bit register.
31
0
RES0
9
evtCount
10
Figure D8-4 AMEVTYPERn_EL0 bit assignments
RES0, [31:10]
Reserved, RES0.
evtCount, bits[9:0]
The event the counter monitors might be fixed at implementation. In this case, the field is read-
only. See C3.4 AMU events on page C3-389.
Configurations
Counters might have fixed event allocation.
Traps and enables
If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are trapped to
EL2.
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1.
Usage constraints
Accessing the AMEVTYPERn_EL0
To access the AMEVTYPERn_EL0:
MRS <Xt>, AMEVTYPERn_EL0 ; Read AMEVTYPERn_EL0 into Xt
MSR AMEVTYPERn_EL0, <Xt> ; Write Xt to AMEVTYPERn_EL0
Register access is encoded as follows:
Table D8-7 AMEVTYPER_EL0 encoding
op0 op1 CRn CRm op2
11 011 1111 1010 <0-4>
This register can also be accessed through the external memory-mapped interface, offset
0x400+4n. In this case, it is read-only.
This register is accessible as follows:
EL0 EL1 EL2 EL3
RO RO RO RO
D8 AArch64 AMU registers
D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D8-490
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