ARM Cortex-A76 Core User Manual

B2.60 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1
The ID_AA64MMFR2_EL1 provides information about the implemented memory model and memory
management support in the AArch64 Execution state.
Bit field descriptions
ID_AA64MMFR2_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
63 04 38 712 1116 15
LSM UAOIESB CnP
RES0
Figure B2-44 ID_AA64MMFR2_EL1 bit assignments
RES0, [63:16]
RES0 Reserved.
IESB, [15:12]
Indicates whether an implicit Error Synchronization Barrier has been inserted. The value is:
0x1 SCTLR_ELx.IESB implicit ErrorSynchronizationBarrier control implemented.
LSM, [11:8]
Indicates whether LDM and STM ordering control bits are supported. The value is:
0x0 LSMAOE and nTLSMD bit not supported.
UAO, [7:4]
Indicates the presence of the User Access Override (UAO). The value is:
0x1 UAO is supported.
CnP, [3:0]
Common not Private. Indicates whether a TLB entry is pointed at a translation table base
register that is a member of a common set. The value is:
0x1 CnP bit is supported.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.60 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core