ARM Cortex-A76 Core User Manual

A8.4 RAS error types
This section describes the RAS error types that are introduced by the RAS extension and supported in the
Cortex-A76 core.
When a component accesses memory, an error might be detected in that memory and then be corrected,
deferred, or detected but silently propagated. The following table lists the types of RAS errors that are
supported in the Cortex-A76 core.
Table A8-2 RAS error types supported in the Cortex-A76 core
RAS error type Definition
Corrected A Corrected Error (CE) is reported for a single-bit ECC error on any protected RAM.
Deferred A Deferred Error (DE) is reported for a double-bit ECC error that affects the data RAM on either the L1 data cache
or the L2 cache.
Uncorrected An Uncorrected Error (UE) is reported for a double-bit ECC error that affects the tag RAM of either the L1 data
cache or the L2 cache. An Uncorrected Error is also reported for external aborts received in response to a store,
data cache maintenance, instruction cache maintenance, TLBI maintenance, or cache copyback of dirty data.
A8 Reliability, Availability, and Serviceability (RAS)
A8.4 RAS error types
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core