ARM Cortex-A76 Core User Manual

A5.4 Translation table walks
When the Cortex-A76 core generates a memory access, the MMU:
1. Performs a lookup for the requested VA, current ASID, current VMID, and current translation regime
in the relevant instruction or data.
2. If there is a miss in the relevant L1 TLB, the MMU performs a lookup for the requested VA, current
ASID, current VMID, and translation regime.
3. If there is a miss in the L2 TLB, the MMU performs a hardware translation table walk.
In the case of a L2 TLB miss, the hardware does a translation table walk as long as the MMU is enabled,
and the translation using the base register has not been disabled.
If the translation table walk is disabled for a particular base register, the core returns a Translation Fault.
If the TLB finds a matching entry, it uses the information in the entry as follows.
The access permission bits determine if the access is permitted. If the matching entry does not pass the
permission checks, the MMU signals a Permission fault. See the Arm
®
Architecture Reference Manual
Armv8, for Armv8-A architecture profile for details of Permission faults, including:
• A description of the various faults.
• The fault codes.
• Information regarding the registers where the fault codes are set.
This section contains the following subsection:
• A5.4.1 AArch64 behavior on page A5-66.
A5.4.1 AArch64 behavior
When executing in AArch64 state at a particular Exception level, you can configure the hardware
translation table walk to use either the 4KB, 16KB, or 64KB translation granule. Program the Translation
Granule bit, TG0, in the appropriate translation control register:
• TCR_EL1.
• TCR_EL2.
• TCR_EL3.
• VTCR_EL2.
For TCR_EL1, you can program the Translation Granule bits TG0 and TG1 to configure the translation
granule respectively for TTBR0_EL1 and TTBR1_EL1, or TCR_EL2 when VHE is enabled.
A5 Memory Management Unit
A5.4 Translation table walks
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A5-66
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core