ARM Cortex-A76 Core User Manual

A4.7 Encoding for power modes
The following table shows the encodings for the supported modes for each core domain P-Channel.
Table A4-2 Core power modes COREPSTATE encoding
Power mode Short name PACTIVE bit
number
PSTATE value
a
Power mode description
Debug recovery DEBUG_RECOV -
0b001010
Logic is off (or in reset), RAM state is retained
and not invalidated when transitioning to On
mode.
On ON 8
0b001000
All powerup.
Core dynamic
retention
FULL_RET 5
0b000101
Logic and RAM state are inoperable but retained.
Off (emulated) OFF_EMU 1
0b000001
On with Warm reset asserted, debug state is
retained and accessible.
Off OFF 0 (implicit)
b
0b000000
All powerdown.
a
PSTATE[5:4] are don't care.
b
It is tied off to 0 and should be inferred when all other PACTIVE bits are LOW. For more information, see the AMBA
®
Low Power Interface Specification Arm
®
Q-
Channel and P-Channel Interfaces.
A4 Power management
A4.7 Encoding for power modes
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core