ARM Cortex-A76 Core User Manual

B5.1 AArch64 register summary
The core has several Advanced SIMD and floating-point system registers in the AArch64 execution
state. Each register has a specific purpose, specific usage constraints, configurations, and attributes.
The following table gives a summary of the Cortex-A76 core Advanced SIMD and floating-point system
registers in the AArch64 execution state.
Table B5-1 AArch64 Advanced SIMD and floating-point system registers
Name Type Reset Description
FPCR RW
0x00000000
See B5.2 FPCR, Floating-point Control Register on page B5-347.
FPSR RW UNKNOWN See B5.3 FPSR, Floating-point Status Register on page B5-349.
MVFR0_EL1 RO
0x10110222
See B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1
on page B5-351.
MVFR1_EL1 RO
0x13211111
See B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1
on page B5-353.
MVFR2_EL1 RO
0x00000043
See B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1
on page B5-355.
B5 Advanced SIMD and floating-point registers
B5.1 AArch64 register summary
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B5-346
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core