B5.1 AArch64 register summary
The core has several Advanced SIMD and floating-point system registers in the AArch64 execution
state. Each register has a specific purpose, specific usage constraints, configurations, and attributes.
The following table gives a summary of the Cortex-A76 core Advanced SIMD and floating-point system
registers in the AArch64 execution state.
Table B5-1 AArch64 Advanced SIMD and floating-point system registers
Name Type Reset Description
FPCR RW
0x00000000
See B5.2 FPCR, Floating-point Control Register on page B5-347.
FPSR RW UNKNOWN See B5.3 FPSR, Floating-point Status Register on page B5-349.
MVFR0_EL1 RO
0x10110222
See B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1
on page B5-351.
MVFR1_EL1 RO
0x13211111
See B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1
on page B5-353.
MVFR2_EL1 RO
0x00000043
See B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1
on page B5-355.
B5 Advanced SIMD and floating-point registers
B5.1 AArch64 register summary
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reserved.
B5-346
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