ARM Cortex-A76 Core User Manual

D3.1 Memory-mapped debug register summary
The following table shows the offset address for the registers that are accessible from the external debug
interface.
For those registers not described in this chapter, see the Arm
®
Architecture Reference Manual Armv8, for
Armv8-A architecture profile.
Table D3-1 Memory-mapped debug register summary
Offset Name Type Width Description
0x000-0x01C
- - - Reserved
0x020
EDESR RW 32 External Debug Event Status Register
0x024
EDECR RW 32 External Debug Execution Control Register
0x028-0x02C
- - - Reserved
0x030
EDWAR[31:0] RO 64 External Debug Watchpoint Address Register
0x034
EDWAR[63:32]
0x038-0x07C
- - - Reserved
0x080
DBGDTRRX_EL0 RW 32 Debug Data Transfer Register, Receive
0x084
EDITR WO 32 External Debug Instruction Transfer Register
0x088
EDSCR RW 32
External Debug Status and Control Register
0x08C
DBGDTRTX_EL0 WO 32 Debug Data Transfer Register, Transmit
0x090
EDRCR WO 32 D3.14 EDRCR, External Debug Reserve Control Register
on page D3-432
0x094
EDACR RW 32 Reserved
0x098
EDECCR RW 32 External Debug Exception Catch Control Register
0x09C
- - - Reserved
0x0A0
- - -
Reserved
0x0A4
- - - Reserved
0x0A8
- - - Reserved
0x0AC
- - -
Reserved
0x0B0-0x2FC
- - - Reserved
0x300
OSLAR_EL1 WO 32 OS Lock Access Register
0x304-0x30C
- - - Reserved
0x310
EDPRCR RW 32 External Debug Power/Reset Control Register
0x314
EDPRSR RO 32
External Debug Processor Status Register
0x318-0x3FC
- - - Reserved
0x400
DBGBVR0_EL1[31:0] RW 64 Debug Breakpoint Value Register 0
0x404
DBGBVR0_EL1[63:32]
D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary
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D3-416
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core