ARM Cortex-A76 Core

B5.8 FPSCR, Floating-Point Status and Control Register
The FPSCR provides floating-point system status information and control.
Bit field descriptions
FPSCR is a 32-bit register.
N
30 29 28 6 5 4 3 2 1
Z C V
31 08 716 1527 26 25 24 23 22 21 20 19 18
Len
AHP
DN
FZ
RMode
Stride
QC IOC
DZC
OFC
UFC
IXC
IDCFZ16
RES0
Figure B5-6 FPSCR bit assignments
N, [31]
Floating-point Negative condition code flag.
Set to 1 if a floating-point comparison operation produces a less than result.
Z, [30]
Floating-point Zero condition code flag.
Set to 1 if a floating-point comparison operation produces an equal result.
C, [29]
Floating-point Carry condition code flag.
Set to 1 if a floating-point comparison operation produces an equal, greater than, or unordered
result.
V, [28]
Floating-point Overflow condition code flag.
Set to 1 if a floating-point comparison operation produces an unordered result.
QC, [27]
Cumulative saturation bit.
This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated after 0 was
last written to this bit.
AHP, [26]
Alternative Half-Precision control bit:
0 IEEE half-precision format selected. This is the reset value.
1 Alternative half-precision format selected.
DN, [25]
Default NaN mode control bit:
B5 Advanced SIMD and floating-point registers
B5.8 FPSCR, Floating-Point Status and Control Register
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