ARM Cortex-A76 Core User Manual

0 NaN operands propagate through to the output of a floating-point operation. This is the
reset value.
1 Any operation involving one or more NaNs returns the Default NaN.
The value of this bit only controls floating-point arithmetic. AArch32 Advanced SIMD
arithmetic always uses the Default NaN setting, regardless of the value of the DN bit.
FZ, [24]
Flush-to-zero mode control bit:
0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant
with the IEEE 754 standard. This is the reset value.
1 Flush-to-zero mode enabled.
The value of this bit only controls floating-point arithmetic. AArch32 Advanced SIMD
arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit.
RMode, [23:22]
Rounding Mode control field:
0b00 Round to Nearest (RN) mode. This is the reset value.
0b01 Round towards Plus Infinity (RP) mode.
0b10 Round towards Minus Infinity (RM) mode.
0b11 Round towards Zero (RZ) mode.
The specified rounding mode is used by almost all floating-point instructions. AArch32
Advanced SIMD arithmetic always uses the Round to Nearest setting, regardless of the value of
the RMode bits.
Stride, [21:20]
RES0 Reserved.
FZ16, [19]
Flush-to-zero mode control bit on half-precision data-processing instructions:
0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant
with the IEEE 754 standard.
1 Flush-to-zero mode enabled.
Len, [18:16]
RES0 Reserved.
RES0, [15:8]
RES0 Reserved.
IDC, [7]
Input Denormal cumulative exception bit. This bit is set to 1 to indicate that the Input Denormal
exception has occurred since 0 was last written to this bit.
RES0, [6:5]
RES0 Reserved.
IXC, [4]
Inexact cumulative exception bit. This bit is set to 1 to indicate that the Inexact exception has
occurred since 0 was last written to this bit.
B5 Advanced SIMD and floating-point registers
B5.8 FPSCR, Floating-Point Status and Control Register
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reserved.
B5-359
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core