UFC, [3]
Underflow cumulative exception bit. This bit is set to 1 to indicate that the Underflow exception
has occurred since 0 was last written to this bit.
OFC, [2]
Overflow cumulative exception bit. This bit is set to 1 to indicate that the Overflow exception
has occurred since 0 was last written to this bit.
DZC, [1]
Division by Zero cumulative exception bit. This bit is set to 1 to indicate that the Division by
Zero exception has occurred since 0 was last written to this bit.
IOC, [0]
Invalid Operation cumulative exception bit. This bit is set to 1 to indicate that the Invalid
Operation exception has occurred since 0 was last written to this bit.
Configurations
There is one copy of this register that is used in both Secure and Non-secure states.
The named fields in this register map to the equivalent fields in the AArch64 FPCR and FPSR.
See B5.2 FPCR, Floating-point Control Register on page B5-347 and B5.3 FPSR, Floating-
point Status Register on page B5-349
.
Usage constraints
Accessing the FPSCR
To access the FPSCR:
VMRS <Rt>, FPSCR ; Read FPSCR into Rt
VMSR FPSCR, <Rt> ; Write Rt to FPSCR
Register access is encoded as follows:
Table B5-8 FPSCR access encoding
spec_reg
0001
Note
The Cortex-A76 core implementation does not support the deprecated VFP short vector feature.
Attempts to execute the associated VFP data-processing instructions result in an UNDEFINED Instruction
exception.
Accessibility
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config RW - - - - -
Access to this register depends on the values of CPACR_EL1.FPEN, CPTR_EL2.FPEN,
CPTR_EL2.TFP, CPTR_EL3.TFP, and HCR_EL2.{E2H, TGE}. For details of which values of these
B5 Advanced SIMD and floating-point registers
B5.8 FPSCR, Floating-Point Status and Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B5-360
Non-Confidential
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