ARM Cortex-A76 Core User Manual

B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down
Register, EL1
Register ERXPFGCDNR_EL1 accesses the ERR<n>PFGCNDR register for the error record selected by
ERRSELR_EL1.SEL.
If ERRSELR_EL1.SEL==0, then ERXPFGCDNR_EL1 accesses the ERR0PFGCDNR register of the
core error record. See B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register
on page B3-302.
If ERRSELR_EL1.SEL==1, then ERXPFGCDNR_EL1 accesses the ERR1PFGCDNR register of the
DSU error record. See the Arm
®
DynamIQ
™
Shared Unit Technical Reference Manual.
Configurations
There are no configuration notes.
Accessing the ERXPFGCDNR_EL1
This register can be read using MRS with the following syntax:
MRS <syntax>
This register can be written using MSR with the following syntax:
MSR <syntax>
This syntax is encoded with the following settings in the instruction encoding:
<systemreg> op0 op1 CRn CRm op2
S3_0_C15_C2_2 11 000 1111 0010 010
Accessibility
This register is accessible in software as follows:
<syntax> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
S3_0_C15_C2_2 x x 0 - RW n/a RW
S3_0_C15_C2_2 x 0 1 - RW RW RW
S3_0_C15_C2_2 x 1 1 - n/a RW RW
n/a Not accessible. Executing the PE at this exception level is not permitted.
Traps and enables
For a description of the prioritization of any generated exceptions, see Exception priority order
in the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions
taken to AArch64 state. Subject to these prioritization rules, the following traps and enables are
applicable when accessing this register.
ERXPFGCDNR_EL1 is accessible at EL3 and can be accessible at EL1 and EL2 depending on
the value of bit[5] in ACTLR_EL2 and ACTLR_EL3. See B2.6 ACTLR_EL2, Auxiliary Control
Register, EL2 on page B2-145 and B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
on page B2-147.
ERXPFGCDNR_EL1 is UNDEFINED at EL0.
B2 AArch64 system registers
B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-203
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core