ARM Cortex-A76 Core User Manual

D7.2 PMPCSSR, Snapshot Program Counter Sample Register
The PMPCSSR is an alias for the PCSR register.
However, unlike the other view of PCSR, it is not sensitive to reads. That is, reads of PMPCSSR through
the PMU snapshot view do not cause a new sample capture and do not change CIDSR, CID2SR, or
VIDSR.
Bit field descriptions
The PMPCSSR is a 64-bit read-only register.
63 0
PC
EL
56 55
606162
RES0
NS
Figure D7-1 PMPCSSR bit assignments
NS, [63]
Non-secure sample.
EL, [62:61]
Exception level sample.
RES0, [60:56]
Reserved, RES0.
PC, [55:0]
Sampled PC.
Configurations
There are no configuration notes.
Usage constraints
Any access to PMPCSSR returns an error if any of the following occurs:
• The core power domain is off.
• DoubleLockStatus() == TRUE.
D7 PMU snapshot registers
D7.2 PMPCSSR, Snapshot Program Counter Sample Register
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D7-473
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core