ARM Cortex-A76 Core User Manual

D9.29 TRCIDR0, ID Register 0
The TRCIDR0 returns the tracing capabilities of the ETM trace unit.
Bit field descriptions
The TRCIDR0 is a 32-bit register.
31 0
COMMOPT
5 4 3 2 110 9 8 7 613 12 111415161724 2330 29 28
TSSIZE
RETSTACK
NUMEVENT
QFILT
QSUPP
CONDTYPE
INSTP0
TRCDATA
TRCBB
TRCCOND
TRCCCIRES0
RES1
Figure D9-27 TRCIDR0 bit assignments
RES0, [31:30]
RES0 Reserved.
COMMOPT, [29]
Indicates the meaning of the commit field in some packets:
1 Commit mode 1.
TSSIZE, [28:24]
Global timestamp size field:
0b01000 Implementation supports a maximum global timestamp of 64 bits.
RES0, [23:17]
RES0 Reserved.
QSUPP, [16:15]
Indicates Q element support:
0b00 Q elements not supported.
QFILT, [14]
Indicates Q element filtering support:
0b0 Q element filtering not supported.
CONDTYPE, [13:12]
Indicates how conditional results are traced:
0b00 Conditional trace not supported.
NUMEVENT, [11:10]
Number of events supported in the trace, minus 1:
0b11 Four events supported.
RETSTACK, [9]
D9 ETM registers
D9.29 TRCIDR0, ID Register 0
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D9-534
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core