C3.2 Accessing the activity monitors
The activity monitors can be accessed by:
• Core system registers.
• Memory-mapped access using the debug APB interface.
C3.2.1 Access enable bit
The access enable bit for traps on accesses to activity monitor registers is required at EL2 and EL3.
In the Cortex-A76 core, the CPUAMEN[4] bit in registers ACTLR_EL2 and ACTLR_EL3 controls the
activity monitor registers enable.
Note
In the Cortex-A76 core, the CPUAMEN[4] bit is RES0 in ACTLR (S) and HACTLR. Activity monitors
are not implemented in AArch32.
C3.2.2 System register access
The core implements activity monitoring in AArch64 and the activity monitors can be accessed using the
MRS and MSR instructions.
C3.2.3 External memory-mapped access
Activity monitors can also be memory-mapped accessed from the APB debug interface.
In this case, the AMU registers just provide debug information and are read-only.
C3 Activity Monitor Unit
C3.2 Accessing the activity monitors
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