ARM Cortex-A76 Core User Manual

C3.2 Accessing the activity monitors
The activity monitors can be accessed by:
• Core system registers.
• Memory-mapped access using the debug APB interface.
C3.2.1 Access enable bit
The access enable bit for traps on accesses to activity monitor registers is required at EL2 and EL3.
In the Cortex-A76 core, the CPUAMEN[4] bit in registers ACTLR_EL2 and ACTLR_EL3 controls the
activity monitor registers enable.
Note
In the Cortex-A76 core, the CPUAMEN[4] bit is RES0 in ACTLR (S) and HACTLR. Activity monitors
are not implemented in AArch32.
C3.2.2 System register access
The core implements activity monitoring in AArch64 and the activity monitors can be accessed using the
MRS and MSR instructions.
C3.2.3 External memory-mapped access
Activity monitors can also be memory-mapped accessed from the APB debug interface.
In this case, the AMU registers just provide debug information and are read-only.
C3 Activity Monitor Unit
C3.2 Accessing the activity monitors
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core