ARM Cortex-A76 Core User Manual

B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register
The VSESR_EL2 provides the syndrome value reported to software on taking a virtual SError interrupt
exception.
Bit field descriptions
VSESR_EL2 is a 64-bit register, and is part of:
• The Exception and fault handling registers functional group.
• The Virtualization registers functional group.
If the virtual SError interrupt is taken to EL1, VSESR_EL2 provides the syndrome value reported in
ESR_EL1.
VSESR_EL2 bit assignments
63 25 24
ISS
23 0
RES0
IDS
Figure B2-85 VSESR_EL2 bit assignments
RES0, [63:25]
RES0 Reserved.
IDS, [24]
Indicates whether the deferred SError interrupt was of an IMPLEMENTATION DEFINED type. See
ESR_EL1.IDS for a description of the functionality.
On taking a virtual SError interrupt to EL1 using AArch64 because HCR_EL2.VSE == 1,
ESR_EL1[24] is set to VSESR_EL2.IDS.
ISS, [23:0]
Syndrome information. See ESR_EL1.ISS for a description of the functionality.
On taking a virtual SError interrupt to EL1 using AArch32 due to HCR_EL2.VSE == 1,
ESR_EL1 [23:0] is set to VSESR_EL2.ISS.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core