ARM Cortex-A76 Core User Manual

Chapter A8
Reliability, Availability, and Serviceability (RAS)
This chapter describes the RAS features implemented in the Cortex-A76 core.
It contains the following sections:
• A8.1 Cache ECC and parity on page A8-102.
• A8.2 Cache protection behavior on page A8-103.
• A8.3 Uncorrected errors and data poisoning on page A8-105.
• A8.4 RAS error types on page A8-106.
• A8.5 Error Synchronization Barrier on page A8-107.
• A8.6 Error recording on page A8-108.
• A8.7 Error injection on page A8-109.
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core