B2.92 SCTLR_EL3, System Control Register, EL3
The SCTLR_EL3 provides top-level control of the system, including its memory system at EL3.
Bit field descriptions
SCTLR_EL3 is a 32-bit register, and is part of the Other system control registers functional group.
This register resets to 0x30C50838.
31 0
EE
2526 20 19 18 12 11 2 14 3
WXN
I C A M
SA
30 29 28 27 24 23 22 21 17 16 15 14 13 10 6 5
RES0
RES1
IESB
Figure B2-76 SCTLR_EL3 bit assignments
RES0, [31:30]
RES0 Reserved.
RES1, [29:28]
RES1 Reserved.
RES0, [27:26]
RES0 Reserved.
EE, [25]
Exception endianness. This bit controls the endianness for:
• Explicit data accesses at EL3.
• Stage 1 translation table walks at EL3.
The possible values are:
0 Little endian.
1 Big endian.
The reset value is determined by the CFGEND configuration signal.
I, [12]
Global instruction cache enable. The possible values are:
0 Instruction caches disabled. This is the reset value.
1 Instruction caches enabled.
C, [2]
Global enable for data and unifies caches. The possible values are:
0 Disables data and unified caches. This is the reset value.
1 Enables data and unified caches.
M, [0]
B2 AArch64 system registers
B2.92 SCTLR_EL3, System Control Register, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-276
Non-Confidential
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