ARM Cortex-A76 Core User Manual

B2.92 SCTLR_EL3, System Control Register, EL3
The SCTLR_EL3 provides top-level control of the system, including its memory system at EL3.
Bit field descriptions
SCTLR_EL3 is a 32-bit register, and is part of the Other system control registers functional group.
This register resets to 0x30C50838.
31 0
EE
2526 20 19 18 12 11 2 14 3
WXN
I C A M
SA
30 29 28 27 24 23 22 21 17 16 15 14 13 10 6 5
RES0
RES1
IESB
Figure B2-76 SCTLR_EL3 bit assignments
RES0, [31:30]
RES0 Reserved.
RES1, [29:28]
RES1 Reserved.
RES0, [27:26]
RES0 Reserved.
EE, [25]
Exception endianness. This bit controls the endianness for:
• Explicit data accesses at EL3.
• Stage 1 translation table walks at EL3.
The possible values are:
0 Little endian.
1 Big endian.
The reset value is determined by the CFGEND configuration signal.
I, [12]
Global instruction cache enable. The possible values are:
0 Instruction caches disabled. This is the reset value.
1 Instruction caches enabled.
C, [2]
Global enable for data and unifies caches. The possible values are:
0 Disables data and unified caches. This is the reset value.
1 Enables data and unified caches.
M, [0]
B2 AArch64 system registers
B2.92 SCTLR_EL3, System Control Register, EL3
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B2-276
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core