ARM Cortex-A76 Core User Manual

B2.90 SCTLR_EL1, System Control Register, EL1
The SCTLR_EL1 provides top-level control of the system, including its memory system, at EL1 and
EL0.
Bit field descriptions
SCTLR_EL1 is a 32-bit register, and is part of the Other system control registers functional group.
This register resets to 0x30D50838.
31 0
MACI
SA
CP15BEN
ITD
SED
UMA
SA0EE
DZE
nTWI
UCT
E0E
UCI
2526 24 23 20 1819 17 16 15 1314 12 11 10 89 7 6 5 34 2 127282930 2122
WXN
nTWE
RES0
RES1
SPAN
IESB
Figure B2-74 SCTLR_EL1 bit assignments
RES0, [31:30]
RES0 Reserved.
RES1, [29:28]
RES1 Reserved.
RES0, [27]
RES0 Reserved.
EE, [25]
Exception endianness. The value of this bit controls the endianness for explicit data accesses at
EL1. This value also indicates the endianness of the translation table data for translation table
lookups. The possible values of this bit are:
0 Little-endian.
1 Big-endian.
ITD, [7]
This field is RAZ/WI.
RES0, [6]
RES0 Reserved.
CP15BEN, [5]
CP15 barrier enable. The possible values are:
0 CP15 barrier operations disabled. Their encodings are UNDEFINED.
B2 AArch64 system registers
B2.90 SCTLR_EL1, System Control Register, EL1
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B2-273
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core