ARM Cortex-A76 Core User Manual

D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0
The PMCEID0 defines which common architectural and common microarchitectural feature events are
implemented.
Bit field descriptions
ID[31:0]
31 08 716 15 12346111230 29 28 27 26 25 24 23 22 21 20 19 18 17 1314 910 5
Figure D4-1 PMCEID0 bit assignments
ID[31:0], [31:0]
Common architectural and microarchitectural feature events that can be counted by the PMU
event counters.
The following table shows the PMCEID0 bit assignments with event implemented or not
implemented when the associated bit is set to 1 or 0. See the Arm
®
Architecture Reference
Manual Armv8, for Armv8-A architecture profile for more information about these events.
Table D4-2 PMU events
Bit Event mnemonic Description
[31] L1D_CACHE_ALLOCATE
L1 Data cache allocate:
0
This event is not implemented.
[30] CHAIN
Chain. For odd-numbered counters, counts once for each overflow of the preceding even-
numbered counter. For even-numbered counters, does not count:
1
This event is implemented.
[29] BUS_CYCLES
Bus cycle:
1
This event is implemented.
[28] TTBR_WRITE_RETIRED
TTBR write, architecturally executed, condition check pass - write to translation table base:
1
This event is implemented.
[27] INST_SPEC
Instruction speculatively executed:
1
This event is implemented.
[26] MEMORY_ERROR
Local memory error:
1
This event is implemented.
[25] BUS_ACCESS
Bus access:
1
This event is implemented.
[24] L2D_CACHE_WB
L2 Data cache Write-Back:
1
This event is implemented.
D4 AArch32 PMU registers
D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core