D9.6 TRCBBCTLR, Branch Broadcast Control Register
The TRCBBCTLR controls how branch broadcasting behaves, and allows branch broadcasting to be
enabled for certain memory regions.
Bit field descriptions
The TRCAUXCTLR is a 32-bit register.
31 08 7
RANGE
9
MODE
RES0
Figure D9-5 TRCBBCTLR bit assignments
RES0, [31:9]
RES0 Reserved.
MODE, [8]
Mode bit:
0 Exclude mode. Branch broadcasting is not enabled in the address range that RANGE
defines.
If RANGE==0 then branch broadcasting is enabled for the entire memory map.
1 Include mode. Branch broadcasting is enabled in the address range that RANGE
defines.
If RANGE==0 then the behavior of the trace unit is constrained UNPREDICTABLE. That
is, the trace unit might or might not consider any instructions to be in a branch
broadcast region.
RANGE, [7:0]
Address range field.
Selects which address range comparator pairs are in use with branch broadcasting. Each bit
represents an address range comparator pair, so bit[n] controls the selection of address range
comparator pair n. If bit[n] is:
0 The address range that address range comparator pair n defines, is not selected.
1 The address range that address range comparator pair n defines, is selected.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCBBCTLR can be accessed through the external debug interface, offset 0x03C.
D9 ETM registers
D9.6 TRCBBCTLR, Branch Broadcast Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-505
Non-Confidential
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