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B2.29 CPUPOR_EL3, CPU Private Operation Register, EL3

The CPUPOR_EL3 provides IMPLEMENTATION DEFINED configuration and control options for the core.

Bit field descriptions

CPUPOR_EL3 is a 64-bit register, and is part of the IMPLEMENTATION DEFINED registers functional group.

Reserved

Figure B2-25 CPUPOR_EL3 bit assignments

Reserved, [63:0]

Reserved for Arm internal use.

Configurations

CPUPOR_EL3 is only accessible in Secure state.

Usage constraints

Accessing the CPUPOR_EL3

The CPUPOR_EL3 can be written only when the system is idle. Arm recommends that you

write to this register after a powerup reset, before the MMU is enabled.

Writing to this register might cause UNPREDICTABLE behaviors. Therefore, Arm strongly

recommends that you do not modify this register unless directed by Arm.

This register is accessible as follows:

This register can be read with the MRS instruction using the following syntax:

MRS <Xt>,<systemreg>

This register can be written with the MSR instruction using the following syntax:

MSR <systemreg>, <Xt>

This syntax is encoded with the following settings in the instruction encoding:

<systemreg> op0 op1 CRn CRm op2

S3_6_C15_8_2 11 110 1111 1000 010

Accessibility

This register is accessible in software as follows:

<systemreg> Control Accessibility

E2H TGE NS EL0 EL1 EL2 EL3

S3_6_C15_8_2 x x 0 - - n/a RW

S3_6_C15_8_2 x 0 1 - - - RW

S3_6_C15_8_2 x 1 1 - n/a - RW

'n/a' Not accessible. The core cannot be executing at this Exception level, so this access is not possible.

B2 AArch64 system registers

B2.29 CPUPOR_EL3, CPU Private Operation Register, EL3

reserved.

B2-184

Non-Confidential

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