ARM Cortex-A76 Core User Manual

B3.5 ERR0MISC0, Error Record Miscellaneous Register 0
The ERR0MISC0 is an error syndrome register. It contains corrected error counters, information to
identify where the error was detected, and other state information not present in the corresponding status
and address error record registers.
Bit field descriptions
ERR0MISC0 is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers
functional group.
63 031
RES0
345619 1827324748 28
WAY UNITINDEX
ARRAY
22
SUBARRAY
2324
BANK
25
SUBBANK
38
CECR
394046
CECO
OFROFO
26
Figure B3-4 ERR0MISC0 bit assignments
[63:48]
Reserved, RES0.
OFO, [47]
Sticky overflow bit, other. The possible values of this bit are:
0 Other counter has not overflowed.
1 Other counter has overflowed.
The fault handling interrupt is generated when the corrected fault handling interrupt is enabled
and either overflow bit is set to 1.
CECO, [46:40]
Corrected error count, other. Incremented for each Corrected error that does not match the
recorded syndrome.
This field resets to an IMPLEMENTATION DEFINED which might be UNKNOWN on a Cold reset. If the
reset value is UNKNOWN, then the value of this field remains UNKNOWN until software initializes it.
OFR, [39]
Sticky overflow bit, repeat. The possible values of this bit are:
0 Repeat counter has not overflowed.
1 Repeat counter has overflowed.
The fault handling interrupt is generated when the corrected fault handling interrupt is enabled
and either overflow bit is set to 1.
CECR, [38:32]
Corrected error count, repeat. Incremented for the first recorded error, which also records other
syndromes, and then again for each Corrected error that matches the recorded syndrome.
This field resets to an IMPLEMENTATION DEFINED which might be UNKNOWN on a Cold reset. If the
reset value is UNKNOWN, then the value of this field remains UNKNOWN until software initializes it.
WAY, [31:28]
B3 Error system registers
B3.5 ERR0MISC0, Error Record Miscellaneous Register 0
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core