ARM Cortex-A76 Core User Manual

D9.23 TRCDEVARCH, Device Architecture Register
The TRCDEVARCH identifies the ETM trace unit as an ETMv4 component.
Bit field descriptions
The TRCDEVARCH is a 32-bit register.
ARCHITECT
31 21 20 19 16 15 0
REVISION ARCHID
PRESENT
Figure D9-21 TRCDEVARCH bit assignments
ARCHITECT, [31:21]
Defines the architect of the component:
0x4 Arm JEP continuation.
0x3B Arm JEP 106 code.
PRESENT, [20]
Indicates the presence of this register:
0b1 Register is present.
REVISION, [19:16]
Architecture revision:
0x02 Architecture revision 2.
ARCHID, [15:0]
Architecture ID:
0x4A13 ETMv4 component.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCDEVARCH can be accessed through the external debug interface, offset 0xFBC.
D9 ETM registers
D9.23 TRCDEVARCH, Device Architecture Register
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reserved.
D9-527
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core