ARM Cortex-A76 Core User Manual

B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register
The ERR0PFGCTLR is the Cortex-A76 node register that enables controlled fault generation.
Bit field descriptions
ERR0PFGCTLR is a 32-bit read/write register.
31 30 6 5 4 2
0
DE
R CE
7
UC
1
CDNEN
29
RES0
Figure B3-6 ERR0PFGCTLR bit assignments
CDNEN, [31]
Count down enable. This bit controls transfers from the value that is held in the
ERR0PFGCDNR into the Error Generation Counter and enables this counter to start counting
down. The possible values are:
0 The Error Generation Counter is disabled.
1 The value that is held in the ERR0PFGCDNR register is transferred into the
Error Generation Counter. The Error Generation Counter counts down.
R, [30]
Restartable bit. When it reaches 0, the Error Generation Counter restarts from the
ERR0PFGCDNR value or stops. The possible values are:
0 When it reaches 0, the counter stops.
1 When it reaches 0, the counter reloads the value that is stored in ERR0PFGCDNR
and starts counting down again.
[29:7]
Reserved, RES0.
CE, [6]
Corrected error generation enable. The possible values are:
0 No corrected error is generated.
1 A corrected error might be generated when the Error Generation Counter is
triggered.
DE, [5]
Deferred Error generation enable. The possible values are:
0 No deferred error is generated.
1 A deferred error might be generated when the Error Generation Counter is
triggered.
B3 Error system registers
B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B3-303
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core