ARM Cortex-A76 Core User Manual

B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1
The MVFR2_EL1 describes the features provided by the AArch64 Advanced SIMD and floating-point
implementation.
Bit field descriptions
MVFR2_EL1 is a 32-bit register.
31 8 7 4 3 0
FPMisc SIMDMisc
RES0
Figure B5-5 MVFR2_EL1 bit assignments
[31:8]
RES0 Reserved.
FPMisc, [7:4]
Indicates support for miscellaneous floating-point features.
0x4 Supports:
• Floating-point selection.
• Floating-point Conversion to Integer with Directed Rounding modes.
• Floating-point Round to Integral Floating-point.
• Floating-point MaxNum and MinNum.
SIMDMisc, [3:0]
Indicates support for miscellaneous Advanced SIMD features.
0x3 Supports:
• Floating-point Conversion to Integer with Directed Rounding modes.
• Floating-point Round to Integral Floating-point.
• Floating-point MaxNum and MinNum.
Configurations
There are no configuration notes.
Usage constraints
Accessing the MVFR2_EL1
To access the MVFR2_EL1:
MRS <Xt>, MVFR2_EL1 ; Read MVFR2_EL1 into Xt
Register access is encoded as follows:
Table B5-6 MVFR2_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0011 010
B5 Advanced SIMD and floating-point registers
B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B5-355
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core