ARM Cortex-A76 Core

Indicates whether the floating-point hardware implementation supports only the Flush-to-zero
mode of operation:
1 Hardware supports full denormalized number arithmetic.
Configurations
There are no configuration notes.
Usage constraints
Accessing the MVFR1_EL1
To access the MVFR1_EL1:
MRS <Xt>, MVFR1_EL1 ; Read MVFR1_EL1 into Xt
Register access is encoded as follows:
Table B5-5 MVFR1_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0011 001
Accessibility
This register is accessible as follows:
EL0 EL1(NS) EL1(S) EL2 EL3 (SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
B5 Advanced SIMD and floating-point registers
B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1
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B5-354
Non-Confidential