ARM Cortex-A76 Core User Manual

Indicates whether the floating-point hardware implementation supports only the Flush-to-zero
mode of operation:
1 Hardware supports full denormalized number arithmetic.
Configurations
There are no configuration notes.
Usage constraints
Accessing the MVFR1_EL1
To access the MVFR1_EL1:
MRS <Xt>, MVFR1_EL1 ; Read MVFR1_EL1 into Xt
Register access is encoded as follows:
Table B5-5 MVFR1_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0011 001
Accessibility
This register is accessible as follows:
EL0 EL1(NS) EL1(S) EL2 EL3 (SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
B5 Advanced SIMD and floating-point registers
B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B5-354
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core