ARM Cortex-A76 Core User Manual

D9.69 TRCSYNCPR, Synchronization Period Register
The TRCSYNCPR controls how often periodic trace synchronization requests occur.
Bit field descriptions
The TRCSYNCPR is a 32-bit register.
31 045
PERIOD
RES0
Figure D9-66 TRCSYNCPR bit assignments
RES0, [31:5]
RES0 Reserved.
PERIOD, [4:0]
Defines the number of bytes of trace between synchronization requests as a total of the number
of bytes generated by both the instruction and data streams. The number of bytes is 2
N
where N
is the value of this field:
• A value of zero disables these periodic synchronization requests, but does not disable other
synchronization requests.
• The minimum value that can be programmed, other than zero, is 8, providing a minimum
synchronization period of 256 bytes.
• The maximum value is 20, providing a maximum synchronization period of 2
20
bytes.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSYNCPR can be accessed through the external debug interface, offset 0x034.
D9 ETM registers
D9.69 TRCSYNCPR, Synchronization Period Register
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reserved.
D9-580
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core