D9.63 TRCSEQRSTEVR, Sequencer Reset Control Register
The TRCSEQRSTEVR resets the sequencer to state 0.
Bit field descriptions
The TRCSEQRSTEVR is a 32-bit register
31 0
RESETSEL
8 7 4 36
RESETTYPE
RES0
Figure D9-60 TRCSEQRSTEVR bit assignments
RES0, [31:8]
RES0 Reserved.
RESETTYPE, [7]
Selects the resource type to move back to state 0:
0 Single selected resource.
1 Boolean combined resource pair.
RES0, [6:4]
RES0 Reserved.
RESETSEL, [3:0]
Selects the resource number, based on the value of RESETTYPE:
When RESETTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When RESETTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by
bits[2:0].
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSEQRSTEVR can be accessed through the external debug interface, offset 0x118.
D9 ETM registers
D9.63 TRCSEQRSTEVR, Sequencer Reset Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-574
Non-Confidential
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