ARM Cortex-A76 Core User Manual

B3.2 ERR0ADDR, Error Record Address Register
The ERR0ADDR stores the address that is associated to an error that is recorded.
Bit field descriptions
ERR0ADDR is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers
functional group.
63
RES0
0
PADDR
40 3962
NS
Figure B3-1 ERR0ADDR bit assignments
NS, [63]
Non-secure attribute. The possible values are:
0 The physical address is Secure.
1 The physical address is Non-secure.
RES0, [62:40]
RES0 Reserved.
PADDR, [39:0]
Physical address.
Configurations
ERR0ADDR resets to UNKNOWN.
When ERRSELR.SEL==0, this register is accessible from B2.38 ERXADDR_EL1, Selected
Error Record Address Register, EL1 on page B2-198.
B3 Error system registers
B3.2 ERR0ADDR, Error Record Address Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core