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ARM Cortex-A76 Core

ARM Cortex-A76 Core
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B3.2 ERR0ADDR, Error Record Address Register
The ERR0ADDR stores the address that is associated to an error that is recorded.
Bit field descriptions
ERR0ADDR is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers
functional group.
63
RES0
0
PADDR
40 3962
NS
Figure B3-1 ERR0ADDR bit assignments
NS, [63]
Non-secure attribute. The possible values are:
0 The physical address is Secure.
1 The physical address is Non-secure.
RES0, [62:40]
RES0 Reserved.
PADDR, [39:0]
Physical address.
Configurations
ERR0ADDR resets to UNKNOWN.
When ERRSELR.SEL==0, this register is accessible from B2.38 ERXADDR_EL1, Selected
Error Record Address Register, EL1 on page B2-198.
B3 Error system registers
B3.2 ERR0ADDR, Error Record Address Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B3-293
Non-Confidential

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