ARM Cortex-A76 Core User Manual

B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1
The DISR_EL1 records the SError interrupts consumed by an ESB instruction.
Bit field descriptions
DISR_EL1 is a 64-bit register, and is part of the registers Reliability, Availability, Serviceability (RAS)
functional group.
AET DFSC
63 32
30
25 24 0
A
EA
RES0
568910121323
IDS
31
Figure B2-31 DISR_EL1 bit assignments, DISR_EL1.IDS is 0
RES0, [63:32]
Reserved, RES0.
A, [31]
Set to 1 when ESB defers an asynchronous SError interrupt. If the implementation does not
include any synchronizable sources of SError interrupt, this bit is RES0.
RES0, [30:25]
Reserved, RES0.
IDS, [24]
Indicates the type of format the deferred SError interrupt uses. The value of this bit is:
0 Deferred error uses architecturally-defined format.
RES0, [23:13]
Reserved, RES0.
AET, [12:10]
Asynchronous Error Type. Describes the state of the core after taking an asynchronous Data
Abort exception. The possible values are:
000 Uncontainable error (UC).
001 Unrecoverable error (UEU).
Note
The recovery software must also examine any implemented fault records to determine the
location and extent of the error.
EA, [9]
Reserved, RES0.
RES0, [8:6]
Reserved, RES0.
DFSC, [5:0]
Data Fault Status Code. The possible values of this field are:
B2 AArch64 system registers
B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core