ARM Cortex-A76 Core User Manual

B5.7 AArch32 register summary
The core has one Advanced SIMD and floating-point system registers in the AArch32 execution state.
The following table gives a summary of the Cortex-A76 core Advanced SIMD and floating-point system
registers in the AArch32 execution state.
Table B5-7 AArch32 Advanced SIMD and floating-point system registers
Name Type Reset Description
FPSCR RW UNKNOWN See B5.8 FPSCR, Floating-Point Status and Control Register
on page B5-358.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for information on
permitted accesses to the Advanced SIMD and floating-point system registers.
B5 Advanced SIMD and floating-point registers
B5.7 AArch32 register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B5-357
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core