ARM Cortex-A76 Core User Manual

B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3
RVBAR_EL3 contains the IMPLEMENTATION DEFINED address that execution starts from after reset.
Bit field descriptions
RVBAR_EL3 is a 64-bit register, and is part of the Reset management registers functional group.
This register is Read Only.
0
Reset Vector Base Address
63
Figure B2-73 RVBAR_EL3 bit assignments
RVBA, [63:0]
Reset Vector Base Address. The address that execution starts from after reset when executing in
64-bit state. Bits[1:0] of this register are 0b00, as this address must be aligned, and bits [63:40]
are 0x000000 because the address must be within the physical address size supported by the
core.
Configurations
There are no configuration notes.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3
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B2-272
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core