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ARM Cortex-A76 Core

ARM Cortex-A76 Core
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D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0
The TRCCIDCVR0 contains a Context ID value.
Bit field descriptions
The TRCCIDCVR0 is a 64-bit register.
63 0
Value
3132
RES0
Figure D9-8 TRCCIDCVR0 bit assignments
RES0, [63:32]
RES0 Reserved.
VALUE, [31:0]
The data value to compare against.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCCIDCVR0 can be accessed through the external debug interface, offset 0x600.
D9 ETM registers
D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D9-508
Non-Confidential

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