B2.37 ERRSELR_EL1, Error Record Select Register, EL1
The ERRSELR_EL1 selects which error record should be accessed through the Error Record system
registers. This register is not reset on a warm reset.
Bit field descriptions
ERRSELR_EL1 is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS)
registers functional group.
63 01
SEL
RES0
Figure B2-33 ERRSELR_EL1 bit assignments
RES0, [63:1]
Reserved,RES0.
SEL, [0]
Selects which error record should be accessed.
0 Select record 0 containing errors from Level 1 and Level 2 RAMs located on the
Cortex-A76 core.
1 Select record 1 containing errors from Level 3 RAMs located on the DSU.
Configurations
There are no configuration notes.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.37 ERRSELR_EL1, Error Record Select Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-197
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