B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1
The CPUPWRCTLR_EL1 provides information about power control support for the core.
Bit field descriptions
CPUPWRCTLR_EL1 is a 32-bit register, and is part of the IMPLEMENTATION DEFINED registers functional
group.
31 7 610 9 0
CORE_PWRDN_EN
4
WFI_RET_CTRL
WFE_RET_CTRL
RES0
3 1
Figure B2-27 CPUPWRCTLR_EL1 bit assignments
RES0, [31:10]
RES0 Reserved.
WFE_RET_CTRL, [9:7]
CPU WFE retention control:
000 Disable the retention circuit. This is the default value, see Table B2-7 CPUPWRCTLR
Retention Control Field on page B2-188 for more retention control options.
WFI_RET_CTRL, [6:4]
CPU WFI retention control:
000 Disable the retention circuit. This is the default value, see Table B2-7 CPUPWRCTLR
Retention Control Field on page B2-188 for more retention control options.
RES0, [3:1]
RES0 Reserved.
CORE_PWRDN_EN, [0]
Indicates to the power controller using PACTIVE if the core wants to power down when it
enters WFI state.
0 No power down requested.
1 A power down is requested.
Table B2-7 CPUPWRCTLR Retention Control Field
Encoding Number of counter ticks
c
Minimum retention entry delay
(System counter at 50MHz-10MHz)
000
Disable the retention circuit Default Condition.
001
2 40ns-200ns
c
The number of system counter ticks required before the core signals retention readiness on PACTIVE to the power controller. The core does not accept a retention
entry request until this time.
B2 AArch64 system registers
B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-188
Non-Confidential
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