Table B2-7 CPUPWRCTLR Retention Control Field (continued)
Encoding Number of counter ticks
c
Minimum retention entry delay
(System counter at 50MHz-10MHz)
010
8 160ns-800ns
011
32 640ns – 3,200ns
100
64 1,280ns-6,400ns
101
128 2,560ns-12,800ns
110
256 5,120ns-25,600ns
111
512 10,240ns-51,200ns
Configurations
There are no configuration notes.
Usage constraints
Accessing the CPUPWRCTLR_EL1
This register can be read using MRS with the following syntax:
MRS <Xt>,<systemreg>
This register can be written using MSR with the following syntax:
MSR <systemreg>, <Xt>
This syntax is encoded with the following settings in the instruction encoding:
<systemreg> op0 op1 CRn CRm op2
S3_0_C15_C2_7 11 000 1111 0010 111
Accessibility
This register is accessible in software as follows:
<systemreg> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
S3_0_C15_C2_7 x x 0 - RW n/a RW
S3_0_C15_C2_7 x 0 1 - RW RW RW
S3_0_C15_C2_7 x 1 1 - n/a RW RW
'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.
Traps and enables
For a description of the prioritization of any generated exceptions, see Synchronous exception
prioritization in the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture
profile for exceptions taken to AArch64 state.
Write access to this register from EL1 or EL2 depends on the value of bit[7] of ACTLR_EL2
and ACTLR_EL3.
c
The number of system counter ticks required before the core signals retention readiness on PACTIVE to the power controller. The core does not accept a retention
entry request until this time.
B2 AArch64 system registers
B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-189
Non-Confidential
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