ARM Cortex-A76 Core User Manual

D7.5 PMSSSR, PMU Snapshot Status Register
The PMSSSR holds status information about the captured counters.
Bit field descriptions
The PMSSSR is a 32-bit read-only register.
31 0
1
NC
RES0
Figure D7-2 PMSSSR bit assignments
RES0, [31:1]
Reserved, RES0.
NC, [0]
No capture. This bit indicates whether the PMU counters have been captured. The possible
values are:
0 PMU counters are captured.
1 PMU counters are not captured.
If there is a security violation, the core does not capture the event counters. The external monitor
is responsible for keeping track of whether it managed to capture the snapshot registers from the
core.
This bit does not reflect the status of the captured Program Counter Sample registers.
The core resets this bit to 1 by a Warm reset but MPSSSR.NC is overwritten at the first capture.
Configurations
There are no configuration notes.
Usage constraints
Any access to PMSSSR returns an error if any of the following occurs:
• The core power domain is off.
• DoubleLockStatus() == TRUE.
D7 PMU snapshot registers
D7.5 PMSSSR, PMU Snapshot Status Register
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D7-476
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core