ARM Cortex-A76 Core User Manual

Chapter B2
AArch64 system registers
This chapter describes the system registers in the AArch64 state.
It contains the following sections:
• B2.1 AArch64 registers on page B2-126.
• B2.2 AArch64 architectural system register summary on page B2-127.
• B2.3 AArch64 implementation defined register summary on page B2-134.
• B2.4 AArch64 registers by functional group on page B2-136.
• B2.5 ACTLR_EL1, Auxiliary Control Register, EL1 on page B2-144.
• B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 on page B2-145.
• B2.7 ACTLR_EL3, Auxiliary Control Register, EL3 on page B2-147.
• B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1 on page B2-149.
• B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2 on page B2-150.
• B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3 on page B2-151.
• B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1 on page B2-152.
• B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2 on page B2-153.
• B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3 on page B2-154.
• B2.14 AIDR_EL1, Auxiliary ID Register, EL1 on page B2-155.
• B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1 on page B2-156.
• B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2 on page B2-157.
• B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3 on page B2-158.
• B2.18 CCSIDR_EL1, Cache Size ID Register, EL1 on page B2-159.
• B2.19 CLIDR_EL1, Cache Level ID Register, EL1 on page B2-161.
• B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1 on page B2-163.
• B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2 on page B2-164.
• B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3 on page B2-165.
• B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1 on page B2-166.
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core