ARM Cortex-A76 Core User Manual

• B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1 on page B2-168.
• B2.25 CPUCFR_EL1, CPU Configuration Register, EL1 on page B2-170.
• B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1 on page B2-172.
• B2.27 CPUPCR_EL3, CPU Private Control Register, EL3 on page B2-180.
• B2.28 CPUPMR_EL3, CPU Private Mask Register, EL3 on page B2-182.
• B2.29 CPUPOR_EL3, CPU Private Operation Register, EL3 on page B2-184.
• B2.30 CPUPSELR_EL3, CPU Private Selection Register, EL3 on page B2-186.
• B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1 on page B2-188.
• B2.32 CSSELR_EL1, Cache Size Selection Register, EL1 on page B2-190.
• B2.33 CTR_EL0, Cache Type Register, EL0 on page B2-191.
• B2.34 DCZID_EL0, Data Cache Zero ID Register, EL0 on page B2-193.
• B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1 on page B2-194.
• B2.36 ERRIDR_EL1, Error ID Register, EL1 on page B2-196.
• B2.37 ERRSELR_EL1, Error Record Select Register, EL1 on page B2-197.
• B2.38 ERXADDR_EL1, Selected Error Record Address Register, EL1 on page B2-198.
• B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1 on page B2-199.
• B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1 on page B2-200.
• B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1 on page B2-201.
• B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1 on page B2-202.
• B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
on page B2-203.
• B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
on page B2-204.
• B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1 on page B2-206.
• B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1 on page B2-207.
• B2.47 ESR_EL1, Exception Syndrome Register, EL1 on page B2-208.
• B2.48 ESR_EL2, Exception Syndrome Register, EL2 on page B2-209.
• B2.49 ESR_EL3, Exception Syndrome Register, EL3 on page B2-210.
• B2.50 HACR_EL2, Hyp Auxiliary Configuration Register, EL2 on page B2-211.
• B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 on page B2-212.
• B2.52 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0 on page B2-214.
• B2.53 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1 on page B2-215.
• B2.54 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1 on page B2-216.
• B2.55 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1 on page B2-218.
• B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1 on page B2-219.
• B2.57 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1 on page B2-221.
• B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1 on page B2-222.
• B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1 on page B2-224.
• B2.60 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1 on page B2-226.
• B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1 on page B2-227.
• B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1 on page B2-229.
• B2.63 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1 on page B2-230.
• B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1 on page B2-231.
• B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 on page B2-233.
• B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 on page B2-235.
• B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1 on page B2-237.
• B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1 on page B2-239.
• B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1 on page B2-241.
• B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 on page B2-243.
• B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245.
• B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1 on page B2-246.
• B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1 on page B2-248.
• B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1 on page B2-250.
• B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1 on page B2-252.
• B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page B2-254.
• B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1 on page B2-256.
B2 AArch64 system registers
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
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B2-124
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core