A1.6 Design tasks
The Cortex-A76 core is delivered as a synthesizable Register Transfer Level (RTL) description in Verilog
HDL. Before you can use the Cortex-A76 core, you must implement it, integrate it, and program it.
A different party can perform each of the following tasks. Each task can include implementation and
integration choices that affect the behavior and features of the core.
Implementation
The implementer configures and synthesizes the RTL to produce a hard macrocell. This task
includes integrating RAMs into the design.
Integration
The integrator connects the macrocell into a SoC. This task includes connecting it to a memory
system and peripherals.
Programming
In the final task, the system programmer develops the software to configure and initialize the
core and tests the application software.
The operation of the final device depends on the following:
Build configuration
The implementer chooses the options that affect how the RTL source files are pre-processed.
These options usually include or exclude logic that affects one or more of the area, maximum
frequency, and features of the resulting macrocell.
Configuration inputs
The integrator configures some features of the core by tying inputs to specific values. These
configuration settings affect the start-up behavior before any software configuration is made.
They can also limit the options available to the software.
Software configuration
The programmer configures the core by programming particular values into registers. The
configuration choices affect the behavior of the core.
A1 Introduction
A1.6 Design tasks
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A1-31
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