ARM Cortex-A76 Core User Manual

B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1
The MVFR1_EL1 describes the features provided by the AArch64 Advanced SIMD and floating-point
implementation.
Bit field descriptions
MVFR1_EL1 is a 32-bit register.
FPFtZ
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
SIMDFMAC FPHP SIMDHP SIMDSP SIMDInt SIMDLS FPDNaN
Figure B5-4 MVFR1_EL1 bit assignments
SIMDFMAC, [31:28]
Indicates whether the Advanced SIMD and floating-point unit supports fused multiply
accumulate operations:
1 Implemented.
FPHP, [27:24]
Indicates whether the Advanced SIMD and floating-point unit supports half-precision floating-
point conversion instructions:
3 Floating-point half precision conversion and data processing instructions
implemented.
SIMDHP, [23:20]
Indicates whether the Advanced SIMD and floating-point unit supports half-precision floating-
point conversion operations:
2 Advanced SIMD half precision conversion and data processing instructions
implemented.
SIMDSP, [19:16]
Indicates whether the Advanced SIMD and floating-point unit supports single-precision
floating-point operations:
1 Implemented.
SIMDInt, [15:12]
Indicates whether the Advanced SIMD and floating-point unit supports integer operations:
1 Implemented.
SIMDLS, [11:8]
Indicates whether the Advanced SIMD and floating-point unit supports load/store instructions:
1 Implemented.
FPDNaN, [7:4]
Indicates whether the floating-point hardware implementation supports only the Default NaN
mode:
1 Hardware supports propagation of NaN values.
FPFtZ, [3:0]
B5 Advanced SIMD and floating-point registers
B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B5-353
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core