ARM Cortex-A76 Core User Manual

B2.47 ESR_EL1, Exception Syndrome Register, EL1
The ESR_EL1 holds syndrome information for an exception taken to EL1.
Bit field descriptions
ESR_EL1 is a 32-bit register, and is part of the Exception and fault handling registers functional group.
31 0
ISS
IL
EC
25 2426
Figure B2-34 ESR_EL1 bit assignments
EC, [31:26]
Exception Class. Indicates the reason for the exception that this register holds information
about.
IL, [25]
Instruction Length for synchronous exceptions. The possible values are:
0 16-bit.
1 32-bit.
This field is 1 for the SError interrupt, instruction aborts, misaligned PC, Stack pointer
misalignment, data aborts for which the ISV bit is 0, exceptions caused by an illegal instruction
set state, and exceptions using the 0x00 Exception Class.
ISS, [24:0]
Syndrome information.
When reporting a virtual SEI, bits[24:0] take the value of VSESRL_EL2[24:0].
When reporting a physical SEI, the following occurs:
• IDS==0 (architectural syndrome).
• AET always reports an uncontainable error (UC) with value 0b000 or an unrecoverable error (UEU)
with value 0b001.
• EA is RES0.
When reporting a synchronous data abort, EA is RES0.
See B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register on page B2-287.
Configurations
This register has no configuration options.
B2 AArch64 system registers
B2.47 ESR_EL1, Exception Syndrome Register, EL1
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B2-208
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core