ARM Cortex-A76 Core

D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5
The PMEVCNTSRn, are captured copies of PMEVCNTRn_EL0, n is 0-5.
When they are captured, the value in PMSSEVCNTRn is unaffected by writes to PMSSEVCNTRn_EL0
and PMCR_EL0.P.
Configurations
There are no configuration notes.
Usage constraints
Any access to PMSSEVCNTRn returns an error if any of the following occurs:
• The core power domain is off.
• DoubleLockStatus() == TRUE.
D7 PMU snapshot registers
D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5
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