ARM Cortex-A76 Core User Manual

A8.6 Error recording
The component that detects an error is called a node. The Cortex-A76 core is a node that interacts with
the DynamIQ Shared Unit node. There is one record per node for the errors detected.
For more information on error recording generated by cache protection, see the Arm
®
Reliability,
Availability, and Serviceability (RAS) Specification, Armv8, for the Armv8-A architecture profile. The
following points apply specifically to the Cortex-A76 core:
• Error recording is only available when the core cache protection is implemented.
• In the Cortex-A76 core, any error that is detected is reported and recorded in the error record
registers:
— B2.37 ERRSELR_EL1, Error Record Select Register, EL1 on page B2-197
— B2.38 ERXADDR_EL1, Selected Error Record Address Register, EL1 on page B2-198
— B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1 on page B2-199
— B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1 on page B2-200
— B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1 on page B2-201
— B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1 on page B2-202
— B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
on page B2-203
— B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
on page B2-204
— B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1
on page B2-206
— B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1 on page B2-207
• There are two error records provided, which can be selected with the ERRSELR_EL1 register:
— Record 0 is private to the core, and is updated on any error in the core RAMs including L1
caches, TLB, and L2 cache.
— Record 1 records any error in the L3 and snoop filter RAMs and is shared between all cores in the
cluster.
• The fault handling interrupt is generated on the nFAULTIRQ[0] pin for L3 and snoop filter errors, or
on the nFAULTIRQ[n+1] pin for core n L1 and L2 errors.
A8 Reliability, Availability, and Serviceability (RAS)
A8.6 Error recording
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A8-108
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core