ARM Cortex-A76 Core

D9.7 TRCCCCTLR, Cycle Count Control Register
The TRCCCCTLR sets the threshold value for cycle counting.
Bit field descriptions
The TRCCCCTLR is a 32-bit register.
31 0
THRESHOLD
12 11
RES0
Figure D9-6 TRCCCCTLR bit assignments
RES0, [31:12]
RES0 Reserved.
THRESHOLD, [11:0]
Instruction trace cycle count threshold.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCCCCTLR can be accessed through the external debug interface, offset 0x038.
D9 ETM registers
D9.7 TRCCCCTLR, Cycle Count Control Register
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